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1. Interrupt  To break into, or between; to stop, or hinder by breaking in upon the course or progress of; to interfere with the current or motion of; to cause a temporary cessation of; as, to interrupt the remarks speaking.
2. Interrupt  To divide; to separate; to break the monotony of; as, the evenness of the road was not interrupted by a single hill.
3. Interrupt  Broken; interrupted.
4. interrupt   interrupt 1. An asynchronous event that suspends normal processing and temporarily diverts the flow of control through an "interrupt handler" routine. Interrupts may be caused by both hardware I/O, timer, machine check and software supervisor, system call or trap instruction. In general the computer responds to an interrupt by storing the information about the current state of the running program; storing information to identify the source of the interrupt; and invoking a first-level interrupt handler. This is usually a kernel level privileged process that can discover the precise cause of the interrupt e.g. if several devices share one interrupt and what must be done to keep operating system tables such as the process table updated. This first-level handler may then call another handler, e.g. one associated with the particular device which generated the interrupt. 2. Under MS-DOS, nearly synonymous with "system call" because the OS and BIOS routines are both called using the INT instruction see interrupt list and because programmers so often have to bypass the operating system going directly to a BIOS interrupt to get reasonable performance. [Jargon File]
5. interrupt  destroy the peace or tranquility of; "Don''t interrupt me when I''m reading"
6. interrupt handler   interrupt handler A routine which is executed when an interrupt occurs. Interrupt handlers typically deal with low-level events in the hardware of a computer system such as a character arriving at a serial port or a tick of a real-time clock. Special care is required when writing an interrupt handler to ensure that either the interrupt which triggered the handler's execution is masked out inhibitted until the handler exits, or the handler is re-entrant so that multiple concurrent invocations will not interfere with each other. If interrupts are masked then the handler must execute as quickly as possible so that important events are not missed. This is often arranged by splitting the processing associated with the event into "upper" and "lower" halves. The lower part is the interrupt handler which masks out further interrupts as required, checks that the appropriate event has occurred this may be necessary if several events share the same interrupt, services the interrupt, e.g. by reading a character from a UART and writing it to a queue, and re-enabling interrupts. The upper half executes as part of a user process. It waits until the interrupt handler has run. Normally the operating system is responsible for reactivating a process which is waiting for some low-level event. It detects this by a shared flag or by inspecting a shared queue or by some other synchronisation mechanism. It is important that the upper and lower halves do not interfere if an interrupt occurs during the execution of upper half code. This is usually ensured by disabling interrupts during critical sections of code such as removing a character from a queue.
7. interrupt list   interrupt list [MS-DOS] The list of all known software interrupt calls both documented and undocumented for IBM PCs and compatibles, maintained and made available for free redistribution by Ralf Brown . As of late 1992, it had grown to approximately two megabytes in length. interrupt priority level The Motorola 68000 family of processors can be at an interrupt priority level from 0 no interrupt in progress up to 7. While the processor is handling an interrupt at one level, it will ignore other interrupts at that level or lower.
8. interrupt request   interrupt request IRQ The name of an input found on many processors which causes the processor to suspend normal instruction execution temporarily and to start executing an interrupt handler routine. Such an input may be either "level sensitive" - the interrupt condition will persist as long as the input is active or "edge triggered" - an interrupt is signalled by a low-to-high or high-to-low transition on the input. Some processors have several interrupt request inputs allowing different priority interrupts.